As feature sizes of integrated circuits continue to shrink to meet performance demands and overall chip dimensions increase, the interconnect structure consumes more of the available power and delay budgets for integrated circuits. As wiring has become more expensive and clock frequencies have increased, designers have investigated three-dimensional integration as a means of reducing signaling across chips.
Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) and system-in-package (SiP) packaging techniques. 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, as examples.
3DICs have multiple layers of active components. The active components can be wired to devices on the same and/or different layers. In one approach, multiple conventional wafers are arranged together in a stack with some means of interconnecting the conventional circuits. Wafers can be bonded face-to-face (i.e., such that the metallizations are adjacent), face-to-back (i.e., such that the metallization layers of one wafer face the substrate of a second wafer) or back-to-back (i.e., such that the substrate of one wafer faces the substrate of a second wafer) using interconnects formed in high-aspect-ratio vias through the device area of the upper wafer. Following bonding of the wafers, the stack is packaged.
An improved three-dimensional integration structure and method are desired.